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direct modulation /waveform generating , 6.1 ghz , fractional - n frequency synthesizer data sheet adf4158 rev. i document feedback information furnished by analog devices is bel ieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2010C 2018 analog devices, inc. all rights reserved. technical support www.analog.com f eatures radio frequency ( rf) bandwidth to 6.1 ghz 25- bit fixed modulus allows sub hertz frequency resolution frequency and p hase modulation capability sawtooth and triangular waveforms in the frequency domain parabolic ramp ramp superimposed with fsk ramp with 2 different sweep rates ramp d elay ramp f requency r eadback ramp i nterruption 2.7 v to 3.3 v power supply separate v p allows extended tuning voltage programmable charge pump currents 3 - wire serial interface digital lock detect power - down mode cycle s li p r eduction for faster lock times switched b andwidth fast lock mode qualified for automotive applications a pplications frequency modulated continuous wave ( fmcw ) r adar communications test equipment g eneral d escription the adf4158 is a 6.1 ghz , fractional - n frequency synthesizer with direct modulation and waveform generation capability. it contains a 25 - bit fixed modulus, allowing sub hertz resolution at 6.1 ghz. it consists of a low noise digital ph ase frequency detector (pfd), a precision charge pump, and a programmable reference divider. there is a sigma - delta ( - ) based fractional interpolator to allow programmable fractional - n division. the int and fra c registers define an overall n - divider as n = int + (frac/2 25 ) . the adf4158 can be used to implement frequency shift keying ( fsk ) and p hase shift k eying (psk) modulation. there are also a num ber of frequency sweep modes available that generate various wav eforms in the frequency domain , for example, sawtooth and triangular waveforms. the ad f4158 features cycle slip reduction circuitry, which leads to faster lock times, without the need for modifications to the loop filter. control of all on - chip registers is via a simple 3 - wire interface. the device operates with a power supply ranging fro m 2.7 v to 3.3 v and can be powered down when not in use. f unctional block diag ram lock detect n-counter cp sw1 reference dat a le tx dat a ce 32-bit dat a register clk ref in a v dd agnd v dd v dd dgnd r div n div dgnd cpgnd dv dd v p r set rf in a rf in b output mux ? + high-z phase frequenc y detec t or adf4158 third-order fractiona l interpol a t or modulus 2 25 fraction reg integer reg csr 2 doubler 5-bit r-counter 2 divider charge pum p muxout 08728-001 fl o switch sw2 figure 1 .
adf4158 data sheet rev. i | page 2 of 35 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and pin function descriptions ...................... 8 typical performance characteristics ............................................. 9 circuit description ......................................................................... 1 1 reference input section ............................................................. 11 rf input stage ............................................................................. 11 rf int divider ........................................................................... 11 25- bit fixed modulus ................................................................ 11 int, frac, and r relationship ............................................... 11 r - counter .................................................................................... 12 phase frequency detector (pfd) and ch arge pump ............ 12 muxout and lock detect ................................................... 12 input shift registers ................................................................... 12 pro gram modes .......................................................................... 12 register maps .................................................................................. 13 frac/int register (r0) map .................................................. 15 lsb fr ac register (r1) map ................................................... 16 r - divider register (r2) map .................................................... 17 function register (r3) map ...................................................... 19 test register (r4) map .............................................................. 21 deviation register (r5) map .................................................... 22 step register (r6) map .............................................................. 23 delay register (r7) map ........................................................... 24 applications information .............................................................. 25 initialization sequence ............................................................... 25 rf synthesizer: a worked example ........................................ 25 reference doubler and reference divider ............................. 25 cy cle slip reduction for faster lock times ........................... 25 modulation .................................................................................. 26 waveform generation ............................................................... 26 other waveforms ....................................................................... 28 external control of ramp steps ............................................... 30 fast lock mode ........................................................................... 32 spur mechanisms ....................................................................... 33 low frequency applications .................................................... 33 filter design adisimpll ....................................................... 33 pcb design guidelines for the chip scale package .............. 33 application of adf4158 in fmcw radar ................................. 34 outline dim ensions ....................................................................... 35 ordering guide ........................................................................... 35 automotive products ................................................................. 35
data sheet adf4158 rev. i | page 3 of 35 revision history 6/2018 rev. h to rev. i updated outline dimensions ........................................................ 35 changes to ordering guide ........................................................... 35 8 /2017 rev. g to rev. h changed cp - 24 - 7 to cp - 24 - 8 ...................................... throughout changes to figure 5 ........................................................................... 8 updated outline dimensions ........................................................ 35 changes to ordering guide ........................................................... 35 3/ 2014 rev. f to rev. g changes to timeout interval section ........................................... 27 2/ 2014 rev. e to rev. f changed ckj to clk, table 3 ......................................................... 6 changed v dd to v dd parameter to dv dd to av dd parameter, table 4 ................................................................................................. 7 changes to 25 - b it fixed modulus section ................................... 11 changes to figure 22 ...................................................................... 14 added - modulator mode section ........................................... 21 changed 12 - bit clock divider value section to 12 - bit clk 2 divider value section ..................................................................... 21 changes to clock divider (div) mode, 12 - bit clk 2 divider value section, and figure 27 ......................................................... 21 changes to frequency deviation section and timeout interval section .............................................................................................. 27 changes to fmcw radar ramp setting s worked example section .............................................................................................. 28 added external control of ramp steps section ......................... 30 changes to figure 42 ...................................................................... 30 changes to interrupt modes and frequency readback section .............................................................................................. 31 added fast lock mode section ..................................................... 32 changes to fast lock timer and register sequences section, fas t lock example section, and fast lock: l oop filter topology section .............................................................................................. 32 3/ 2013 rev. d to re v. e changes to figure 7, figure 8, figure 9, and figure 10 ................ 9 changes to figure 22 ...................................................................... 14 changes to negative bleed current section, readback to muxout section, and figu re 27 ................................................ 21 changes to figure 28 ...................................................................... 22 changes to fmcw radar ramp settings worked example section .............................................................................................. 27 6/ 2012 rev. c to rev. d changes to table 3 and figure 3 ..................................................... 6 added figure 4; renumbered sequentially ................................... 6 added negative bleed current section ........................................ 21 changes to fi gure 27 ...................................................................... 21 12/ 2011 rev. b to rev. c changes to features section ............................................................ 1 changes to figure 6 caption and figure 9 caption ..................... 9 changes to figure 11 ...................................................................... 10 changes to figure 19 ...................................................................... 1 2 changes to figure 20 ...................................................................... 1 3 changed 12 - bit mod divider section to 12 - bit clk 1 divider section .............................................................................................. 1 7 changes to 12 - bit clk 1 divider section ..................................... 1 7 changes to figure 24 ...................................................................... 1 8 changes to delay clock select section and figure 29 ............... 2 4 changes to timeout interval section ........................................... 2 7 changes to fmcw radar ramp settings worked example section .............................................................................................. 2 8 changes to delayed start, examp le section and delay between ramps, example section ................................................................ 2 9 changes to fast - lock timer and register sequences section and fast lock: an example section ............................................. 3 2 changes to ordering guide ........................................................... 35 added automotive products section ........................................... 35 9/ 2011 rev. a to rev. b changes to nois e characteristics parameter ................................. 3 7/ 2011 rev. 0 to rev. a changes to figure 21 ...................................................................... 13 changes to figure 25 ...................................................................... 19 changes to 12 - bit clock divider value section ......................... 20 changes to figure 28 ...................................................................... 22 changes to fmcw radar ramp settings worked example section .............................................................................................. 26 a dded ramp program ming sequence section, and a dded other waveforms heading ............................................................ 2 7 changes to figure 36 ...................................................................... 28 added ramp complete signal to muxout section and changes to figure 40 ...................................................................................... 29 added figure 42; renumbered sequentially ............................... 30 changes to figure 45 ...................................................................... 31 changes to figure 46 ...................................................................... 33 4/ 2010 revision 0: initial version
adf4158 data sheet rev. i | page 4 of 35 specifications av dd = dv dd = 2.7 v to 3.3 v, v p = av dd to 5.5 v, agnd = dgnd = 0 v, t a = t min to t max , dbm referred to 50 ?, unless otherwise noted. table 1. c version 1 parameter min typ max unit test conditions/comments rf characteristics rf input frequency (rf in ) 0.5 6.1 ghz ? 10 dbm min imum to 0 dbm max imum ; for lowe r frequencies, ensure slew rate (sr) > 400 v/s ?15 dbm min imum to 0 dbm max imum for 2 ghz to 4 ghz rf input frequency reference characteristics ref in input frequency 10 260 mhz for f < 10 mhz, use a dc - coupled cmos - compatible square wave, s lew rate > 25 v/s 16 mhz if an internal reference doubler is enabled ref in input sensitivity 0.4 av dd v p -p biased at av dd /2 2 ref in input capacitance 10 pf ref in input current 100 a phase detector phase detector frequency 3 32 mhz charge pump i cp sink/source programmable high value 5 ma with r set = 5.1 k low value 312.5 a absolute accuracy 2.5 % with r set = 5.1 k r set range 2.7 10 k i cp three - state leakage current 1 na sink and source current matching 2 % 0.5 v < v cp < v p C 0.5 v i cp vs. v cp 2 % 0.5 v < v cp < v p C 0.5 v i cp vs. tem perature 2 % v cp = v p /2 logic inputs v inh , input high voltage 1.4 v v inl , input low voltage 0.6 v i inh /i inl , input current 1 a c in , input capacitance 10 pf logic outputs v oh , output high voltage 1.4 v open - drain output ch osen; 1 k pull - up to 1.8 v v oh , output high voltage v dd ? 0.4 v cmos output chosen i oh , output high current 100 a v ol , output low voltage 0.4 v i ol = 500 a power supplies av dd 2.7 3.3 v dv dd av dd v p av dd 5.5 v i dd 23 32 ma
data sheet adf4158 rev. i | page 5 of 35 c version 1 parameter min typ max unit test conditions/comments n oise characteristics normalized phase noise floor ( pn synth ) 4 ? 216 dbc/hz pll loop ban dwidth = 500 khz ; measured at 100 khz offset normalized 1/f noise (pn 1_f ) 5 ?110 dbc/hz 100 khz offset; normalized to 1 g h z phase noise performance 6 at vco output 580 5 mhz output 7 ? 93 dbc/hz at 5 khz offset, 32 mhz pfd frequency 1 operating temperature for c version: ?40c to +125c. 2 ac coupling ensures av dd /2 bias. 3 guaranteed by design. sample tested to ensure complianc e. 4 the synthesizer phase noise floor is estimated by measuring the in - band phase noise at the output of the vco and subtracting 20 log(n) (where n is the n divider value) and 10 log(f pfd ). pn synth = pn tot ? 10 log(f pfd ) ? 20 log(n). 5 the pll phase noise is composed of 1/f (flicker) noise plus the normalized pll noise floor. the formula for calculating the 1/f noise contributio n at an rf frequency, f rf , and at a frequency offset f is given by pn = p n 1_f + 10 log(10 khz/f) + 20 log( f rf /1 ghz). both the nor malized phase noise floor and flicker noise are modeled in adisimpll ? . 6 the phase noise is measured with the eval - adf4158 eb1z and the agilent e5052a phase noise system. 7 f refin = 128 mhz; f pfd = 32 mhz; offset frequency = 5 khz; rf out = 5805 mhz; int = 181; frac = 13631488; loop bandwidth = 100 khz . timing specification s av dd = dv dd = sdv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = sdgnd = 0 v; t a = t min to t max , dbm referred to 50 ?, unless otherwise noted . tab le 2. write timing parameter limit at t min to t max ( c version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clk setup tim e t 3 10 ns min data to cl k hold time t 4 25 ns min cl k high duration t 5 25 ns min cl k low duration t 6 10 ns min cl k to le setup time t 7 20 ns min le pulse width write timing diagram clk d at a le le db31 (msb) db30 db1 (contro l bit c2) db2 (contro l bit c3) db0 (lsb) (contro l bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 08728-026 figure 2 . write timing diagram
adf4158 data sheet rev. i | page 6 of 35 table 3. read timing parameter limit at t min to t max (c version) unit test conditions/comments t 1 20 ns min tx data setup time t 2 20 ns min clk setup time to data (on muxout) t 3 25 ns min clk high duration t 4 25 ns min clk low duration t 5 10 ns min clk to le setup time read timing diagram clk muxout le db36 db35 db1 db2 db0 08728-226 t 1 t 2 tx data notes 1. le should be kept high during readback. t 4 t 5 t 3 figure 3 . read timing diagram 100a 1.5v i ol i oh to output pin c l 10pf 100a 08728-004 figure 4 . load circuit for muxout timing, c l = 10 pf
data sheet adf4158 rev. i | page 7 of 35 absolute maximum rat ings t a = 25c, gnd = agnd = dgnd = sdgnd = 0 v, v dd = av dd = dv dd = sdv dd , unless otherwise noted. table 4. parameter rating v dd to gnd ? 0.3 v to +4 v d v dd to a v dd ? 0.3 v to +0.3 v v p to gnd ? 0.3 v to +5.8 v v p to v dd ? 0.3 v to +5.8 v digital i/o voltage to gnd ? 0.3 v to v dd + 0.3 v analog i/o voltage to gnd ? 0.3 v to v dd + 0.3 v ref in , rf in to gnd ? 0.3 v to v dd + 0.3 v operating temperature range industrial (c version ) ?40 c to +125c storage temperature range ? 65c to +125c maximum junction temperature 150c lfcsp ja thermal impedance (paddle soldered ) 30.4c/w reflow sold ering peak temperature 260c time at peak temperature 40 sec stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
adf4158 data sheet rev. i | page 8 of 35 pin configuration an d pin f unction descriptions cpgnd agnd agnd rf in b rf in a av dd data le muxout sdv dd clk ce av dd av dd ref in sdgnd tx data dgnd sw2 v p r set cp sw1 dv dd 08728-003 2 1 3 4 5 6 18 17 16 15 14 13 8 9 10 11 7 12 20 19 21 22 23 24 adf4158 top view (not to scale) notes 1. the lfcsp has an exposed paddle that must be connected to gnd. figure 5 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 cpgnd charge pump ground. this is the ground return path for the charge pump. 2, 3 agnd analog ground. this is the ground return path of the prescaler. 4 rf in b complement ary input to the rf prescaler. decouple this point to the ground plane with a small bypass capacitor, typically 100 pf. 5 rf in a input to the rf prescaler. this small signa l input is normally ac - coupled from the vco. 6, 7, 8 av dd positive power supply for the rf section. place d ecoupling capacitors to the digital ground plane as close as possible to this pin. av dd must have the same voltage as dv dd . 9 ref in reference input . this is a cmos input with a nominal threshold of v dd /2 and an equ ivalent input resistance of 100 k . it can be driven from a ttl or cmos crystal oscillator, or it can be ac - coupled. 10 dgnd digital ground. 11 sdgnd digital - modulator ground. ground return path for the - m odulator. 12 tx data t x data pin. provide d ata to be transmitted in fsk or psk mode on this pin. 13 ce chip enable. a logic l ow on this pin powers down the device and puts the charge pump output into three - state mode. 14 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the shift register on the clk rising edge. this input is a high impedance cmos input. 15 data serial data input. the serial data is loaded msb first with the three lsbs being the control bits. this input is a high impedance cmos input. 16 le load enable, cmos input. when le is high, the data stored in the shift registers is loaded into one of the eight latches, with the latch being selected using the control bits. 17 muxout multiplexer output. this pin allows either the rf lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 18 sdv dd power supply pin for the digital - modulator. this pin s hould be the same voltage as av dd . place d ecoupling capacitors to the ground plane as close as possible to this pin. 19 dv dd positive power supply for the digital section. place d ecoupling capacito rs to the digital ground plane as close as possible to this pin. dv dd must have the same voltage as av dd . 20 , 21 sw1, sw2 switches for fast lock. 22 v p charge pump power supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5.5 v. 23 r set connecting a resistor between this pin and ground sets the maximum charge pump output current. the relationship between i cp and r set is set cpmax r i 5 . 25 = i cpmax = 5 ma. r set = 5.1 k . 24 cp c harge pump output. when enabled, this provides i cp to the external loop filter, which in turn drives the external vco. 25 epad exposed paddle. the lfcsp has an exposed paddle that must be connected to gnd.
data sheet adf4158 rev. i | page 9 of 35 typical p erformance character istics ?160 ?140 ?120 ?100 ?80 ?60 ?40 1k 10k 100k 1m 10m phase noise (dbc/hz) frequenc y offset (hz) 08728-035 figure 6 . phase noise at 5805 mhz, pfd = 32 mhz, loop bandwidth = 100 khz 5.78 5.79 5.80 5.81 5.82 5.83 5.84 5.85 5.86 ?0.025 ?0.015 ?0.005 0.005 0.015 0.025 frequenc y (ghz) time (s) 08728-036 figure 7 . triangular waveform , pfd = 32 mhz, int = 181, frac = 0, dev offset = 4, dev word = 20 972, step word = 200, clk 2 d ivider = 10, clk 1 divider = 125 5.75 5.77 5.79 5.81 5.83 5.85 5.87 ?0.010 ?0.005 0 0.005 0.010 frequenc y (ghz) time (s) 08728-037 figure 8 . sawtooth waveform , pfd = 32 mhz, int = 181, frac = 0, dev offset = 4, dev word = 20972, step word = 200, clk 2 divider = 10, clk 1 divider = 125 5.76 5.77 5.78 5.79 5.80 5.81 5.82 5.83 5.84 5.85 5.86 5.87 frequenc y (ghz) time (s) ?0.010 ?0.005 0 0.005 0.010 08728-039 figure 9 . delay between ramps for sawtooth wavefor m , pfd = 32 mhz, int = 181, frac = 0, dev offset = 4, dev word = 20972, step word = 200, clk 2 divider = 10, clk 1 divider = 125, del start word = 1025 5.76 5.77 5.78 5.79 5.80 5.81 5.82 5.83 5.84 5.85 5.86 0 0.005 0.010 time (s) frequenc y (ghz) 0.015 0.020 no del a y del a y 08728-040 figure 10 . de layed start of triangular burs t , pfd = 32 mhz, int = 181, frac = 0, dev offset = 4, dev word = 20972, step word = 200, clk 2 divider = 10, clk 1 divider = 125, del start word = 1000 5.790 5.792 5.794 5.796 5.798 5.800 5.802 5.804 5.806 5.808 5.810 ?0.010 0.010 ?0.005 0.005 0 frequenc y (ghz) time (s) 08728-041 figure 11 . dual ramp rate waveform , pf d = 32 mhz, int = 181, frac = 0, ramp 1: dev offset = 3, dev word = 16777, step word = 100, ramp 2: dev offset = 3, dev word = 20792, step word = 80
adf4158 data sheet rev. i | page 10 of 35 5.7995 5.7996 5.7997 5.7998 5.7999 5.8000 5.8001 5.8002 5.8003 5.8004 frequenc y (ghz) ?0.010 0.010 ?0.005 0.005 0 time (s) 08728-042 figure 12 . fsk superimposed on rising edge of triangular waveform; ramp sett ings: pfd = 32 mhz, int = 181, frac = 0, dev offset = 4, dev word = 20972, step word = 200, clk div = 10, clk 1 divider = 125 ; fsk settings : dev offset = 3, dev word = 4194 5.79975 5.79980 5.79985 5.79990 5.79995 5.80005 5.80000 5.80010 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequenc y (ghz) time (ms) 08728-044 figure 13 . fsk; settings: frequency deviation = 100 kh z, data rate = 3 khz ?30 ?25 ?20 ?15 ?10 ?5 0 0.185 1.185 2.185 3.185 4.185 5.185 6.185 7.185 power (dbm) frequenc y (ghz) 08728-128 figure 14 . rf in sensitivit y - average over temp erature and v dd ?8 ?6 ?4 ?2 i cp (ma) 0 2 4 6 0 1 2 3 v cp (v) 4 5 6 08728-046 figure 15 . charge pump output characteristics
data sheet adf4158 rev. i | page 11 of 35 circuit description reference input sect ion the reference inpu t stage is shown in figure 16 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power - down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power - down. buffer t o r-counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down contro l 08728-027 figure 16 . reference input stage rf input stage the rf input stage is shown in figure 17 . it is followed by a 2 - stage limiting amplifier to generate the current - mode logic (cml) clock levels need ed for the prescaler. bias gener a t or 1.6v agnd a v dd 2k? 2k? rf in b rf in a 08728-015 figure 17 . rf input stage rf int divider the rf int cmos counter allows a division ratio in the pll feedback counter. division ratios from 23 to 4095 are allowed. 25-b it fixed modulus the adf4158 has a 25 - bit fixed modulus. this allows output frequencies to be spaced with a resolution of f res = f pfd /2 25 (1) where f pfd is the frequency of the p hase frequency detector (pfd). for example , with a pfd frequency of 10 mhz, frequency steps of 0.298 hz are possible. due to the architecture of the - modulator, there is a fixed + (f pfd /2 26 ) offset on the vco output. to remove this offset, see the - modulator mode section. int, frac , and r relationship the int and frac values, in conjunc tio n with the r - counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (pfd). the rf vco frequency (rf out ) equation is rf out = f pfd ( int + ( frac/2 25 )) (2 ) w here : rf out is the output frequency o f external volta ge controlled oscillator (vco). i nt is the preset divide ratio of binary 12 - bit counter (23 to 4095). frac is the numerator of the fractional division (0 to 2 25 ? 1). f pfd = ref in [(1 + d )/( r (1 + t ))] ( 3 ) where: ref in is the reference input frequency. d is the ref in doubler bit (0 or 1) . r is the preset divide ratio of the binary, 5 - bit, programmable reference counter (1 to 32). t is the ref in divide - by - 2 bit (0 or 1). third-order fractiona l interpol a t or frac v alue mod reg int reg rf n-divider n = int + frac/mod from rf input s t age t o pfd n-counter 08728-016 figure 18 . rf n- divider
adf4158 data sheet rev. i | page 12 of 35 r - counter the 5 - bit r - counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 32 are allowed. phase fr equency detector (pf d) and charge pump the pfd takes inputs from the r - counter and n - counter and produces an output proportional to the phase and frequency difference between them. figure 19 s hows a simplified schematic of the pfd . the pfd includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and gives a consistent reference spur level. u3 clr2 q2 d2 u2 down u p high high c p ?in +in charge pum p del a y clr1 q1 d1 u1 08728-017 figure 19 . pfd simplified schematic muxout and lock dete ct the output multiplexer on the adf4158 allows the user to access various internal poin ts on the chip. the state of muxout is controlled by the m4, m3, m2, and m1 bits ( see figure 23 ). figure 20 shows the muxout section in block diagram form. muxout dv dd three-state output n-divider output dv dd dgnd dgnd r-divider output digital lock detect serial data output clk divider output r-divider/2 n-divider/2 fast-lock switch readback to muxout control mux 08728-009 figure 20 . muxout sc hematic input shift register s the adf4158 digita l section includes a 5 - bit rf r - counter, a 12- bit rf n - counter, and a 25 - bit frac counter. data is clocked into the 32 - bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of eight latches on the rising edge of le. the destination latch is determined by the state of the thre e control bits (c3, c2, and c1) in the shift register. these are the three lsbs db2, db1, and db0 as shown in figure 2 . the truth table for these bits is shown in table 6 . figure 21 and figure 22 show a summary of how the latches are programmed. program modes table 6 and figure 23 through figure 30 show how to set up the program m odes in the adf4158 . several settings in the adf4158 are double buffered. these include the lsb fractional value, r - counter value, reference doubler , current setting , and rdiv2 . this means that two events must occur bef ore the part uses a new value for any of the double - buffered settings. first, the new value is latched into the device by writing to the appropriate register. second, a new write mu st be performed on register r0. for example, updating the fractional value can involve a write to the 13 lsb bits in r1 and the 12 msb bits in r0. r1 sh ould be written to first, followed by the write to r0. the frequency change begins after the write to r0. double buffering ensures that the bits written to in r1 do not take effect until after the write to r0. table 6 . c3, c2, and c 1 truth table control bits c3 c2 c1 register 0 0 0 r0 0 0 1 r1 0 1 0 r2 0 1 1 r3 1 0 0 r4 1 0 1 r5 1 1 0 r6 1 1 1 r7
data sheet adf4158 rev. i | page 13 of 35 register maps db31 control bits 12-bit msb fractional value (frac) 12-bit integer value (int) muxout control db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 m4 r1 m3 m2 m1 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 f25 f24 f23 f22 f21 f20 f19 f18 f17 f16 f15 f14 c3(0) c2(0) c1(0) ramp on frac/int register (r0) db31 control bits reserved 13-bit lsb fractional value (frac) (dbb) reserved db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 0 0 0 0 0 0 0 0 0 0 0 0 c3(0) c2(0) c1(1) lsb frac register (r1) db31 reserved notes 1. dbb = double-buffered bit(s). power-down pd polarity ldp counter reset cp three-state control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns1 u12 0 0 rm2 rm1 pe1 fe1 u11 u10 u9 u8 u7 c3(0) c2(1) c1(1) function register (r3) db31 12-bit clk 1 divider 5-bit r-counter reserved csr en reserved prescaler rdiv2 dbb cp current setting reference doubler dbb control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 cr1 cpi4 cpi3 cpi2 cpi1 0 p1 u2 u1 r5 r4 r3 r2 r1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(0) r-divider register (r2) dbb dbb sd reset n sel reserved ramp mode psk enable fsk enable 08728-010 figure 21 . register summary 1
adf4158 data sheet rev. i | page 14 of 35 db3 1 contro l bits 20-bit ste p word db3 0 db2 9 db2 8 db2 7 db2 6 db2 5 db2 4 db2 3 db2 2 db2 1 db2 0 db1 9 db1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 sse 1 s 2 0 s 1 9 s 1 8 s 1 7 s 1 6 s 1 5 s 1 4 s 1 3 s 1 2 s 1 1 s 1 0 s 9 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 c 3 ( 1) c 2 ( 1) c 1 ( 0 ) ste p register (r6) db3 1 c o n t r o l b i t s 12-b i t d el a y st ar t d i vi d er rese r ved db3 0 db2 9 db2 8 db2 7 db2 6 db2 5 db2 4 db2 3 db2 2 db2 1 db2 0 db1 9 db1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 rdf 1 rd1 dc1 d se 1 d s 1 2 d s 1 1 d s 1 0 d s 9 d s 8 d s 7 d s 6 d s 5 d s 4 d s 3 d s 2 d s 1 c 3 ( 1) c 2 ( 1) c 1 ( 1 ) del a y register (r7) rese r ved ste p se l de l s t art en de l clk se l ram p de l ram p de l f l r eser ved db3 1 12-bit clk 2 divider v alue c o n t r o l b i t s db3 0 db2 9 db2 8 db2 7 db2 6 db2 5 db24 db23 db2 2 db2 1 db2 0 db1 9 db1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 l s 1 s5 s4 s3 s2 s1 0 nb2 nb1 r2 r1 c 2 c 1 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 c 3 ( 1 ) c 2 ( 0 ) c 1 ( 0 ) c l k d i v mo d e read- back t o muxout 0 0 0 0 db3 1 16-bit devi a tion word contro l bits db3 0 db2 9 db2 8 db2 7 db2 6 db2 5 db2 4 db2 3 db2 2 db2 1 db2 0 db1 9 db1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 t r 1 p r 1 i 2 i 1 f r e 1 r 2 e 1 d s 1 d o 4 d o 3 d o 2 d o 1 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 c 3 ( 1 ) c 2 ( 0 ) c 1 ( 1) devi a tion register (r5) test register (r4) d 4 d 3 d 2 d 1 4-bit dev offset word dev se l ram p 2 en fsk ram p en interrupt p ar ram p tx ram p clk rese r ved le se l rese r ved 08728- 1 10 neg bleed current - modulator mode figure 22 . register summa ry 2
data sheet adf4158 rev. i | page 15 of 35 frac/int register (r 0) map with register r0 db [2: 0] set to [0, 0, 0], the on - chip frac/ int register is programmed as shown in figure 23. ramp o n setting db31 to 1 enables the ramp, setting db31 to 0 disables the ramp. mu xout control the on - chip multiplexer is controlled by db[30 :27] on the adf4158 . see figure 23 for the truth table. 12- bit integer value (int) these 12 bits control what is loaded as the int value. this is used to determine the overall feedback division factor. it is used in equation 2 . see the i n t, f r ac , and r relationship section for more informatio n. 12- bit msb fractional value (frac) these 12 bits, along with bits db[27:15] in the lsb frac register ( register r1), control what is loaded as the frac value into the fractional interpolator. this is part of what determines the overall feedback division factor. it is also used in equation 2 . these 12 bits are the most significant bits (msb) of the 25 - bit frac value, and bits db[27:15] in the lsb frac register ( register r1) are the least significant bits (lsb). see the rf synthesizer: a worked example section for more information. db31 control bits 12-bit msb fractional value (frac) 12-bit integer value (int) muxout control db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r1 m4 m3 m2 m1 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 f25 f24 f23 f22 f21 f20 f19 f18 f17 f16 f15 f14 c3(0) c2(0) c1(0) ramp on m 4 m 3 m 2 m 1 output 0 0 0 0 t hr ee - s t a t e o u t p u t 0 0 0 1 d v dd 0 0 1 0 d g n d 0 0 1 1 r - di v i d e r out p u t 0 1 0 0 n - di v i d e r out p u t 0 1 0 1 reserved 0 1 1 0 digi t a l lock detect 0 1 1 1 ser i a l d a t a out p ut 1 0 0 0 r ese r ve d 1 0 0 1 r ese r ve d 1 0 1 0 clk di v i d e r output 1 0 1 1 r ese r ve d 1 1 0 0 fast-lock switch 1 1 0 1 r - d i v i d e r /2 1 1 1 0 n - d i v i d e r /2 1 1 1 1 r eadback to muxout r1 ramp on 0 ramp disabled ramp enabled 1 f25 f24 .......... f15 f14 msb fractional value (frac)* 0 0 ..... . ... . 0 0 0 0 0 ..... . ... . 0 1 1 0 0 ..... . ... . 1 0 2 0 0 ..... . ... . 1 1 3 . . ..... . ... . . . . . . ..... . ... . . . . . . ..... . ... . . . . 1 1 ..... . ... . 0 0 40 9 2 1 1 ..... . ... . 0 1 40 9 3 1 1 ..... . ... . 1 0 40 9 4 1 1 ..... . ... . 1 1 40 9 5 n 12 n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 integer v a lue ( i nt) 0 0 0 0 0 0 0 1 0 1 1 1 23 0 0 0 0 0 0 0 1 1 0 0 0 24 0 0 0 0 0 0 0 1 1 0 0 1 25 0 0 0 0 0 0 0 1 1 0 1 0 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 1 1 1 0 1 40 9 3 1 1 1 1 1 1 1 1 1 1 1 0 40 9 4 1 1 1 1 1 1 1 1 1 1 1 1 40 9 5 *the frac value is made up of the 12-bit msb stored in register r0, and the 13-bit lsb register stored in register r1. frac value = 13-bit lsb + 12-bit msb 2 13 . 08728-011 figure 23 . frac/int register (r0) map
adf4158 data sheet rev. i | page 16 of 35 lsb frac register (r 1) map with register r1 db [ 2: 0] set to [0, 0, 1], the on - chip lsb frac register is programmed as shown in figure 24. 13- bit lsb frac value these 13 bits, alo ng with bits db[14:3] in the frac /int register ( register r0), control what is loaded as the frac value into the fractional interpolator. this is part of what determines the overall feedback division factor. it is also used in equation 2 . these 13 bits are the least significant bits (lsb) of the 25 - bit frac value, and bits db[14:3] in the int/frac register are the most significant bits (msb) . see the rf synthesizer: a worked example section for more information. reserved bits all reserved bits should be set to 0 for normal operation. db31 control bits reserved 13-bit lsb fractional value (frac) (dbb) reserved db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 0 0 0 0 0 0 0 0 0 0 0 0 c3(0) c2(0) c1(1) f13 f12 .......... f2 f1 lsb fractional value (frac)* 0 0 ..... . ... . 0 0 0 0 0 ..... . ... . 0 1 1 0 0 ..... . ... . 1 0 2 0 0 ..... . ... . 1 1 3 . . ..... . ... . . . . . . ..... . ... . . . . . . ..... . ... . . . . 1 1 ..... . ... . 0 0 81 8 8 1 1 ..... . ... . 0 1 81 8 9 1 1 ..... . ... . 1 0 81 9 0 1 1 ..... . ... . 1 1 81 9 1 *the frac value is made up of the 12-bit msb stored in register r0, and the 13-bit lsb register stored in register r1. frac value = 13-bit lsb + 12-bit msb 2 13 . 08728-012 notes 1. dbb = double-buffered bits. figure 24 . lsb frac register (r1) map
data sheet adf4158 rev. i | page 17 of 35 r - divider register (r2 ) map with register r2 db [2 : 0] set to [0, 1, 0], the on - chip r - divider register is programmed as shown in figure 25. reserved bits all reserved bits should be set to 0 for normal operation. csr enable setting this bit to 1 enables cycle slip reduction. this is a method for i mproving lock times. note that the signal at the pfd must have a 50% duty cycle in order for cycle slip reduction to work. in addition, the charge pump current setting must be set to a minimum. see the cycle slip reduction for faster lock times section for more information. also n ote that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (db6 in register r3). it cannot be used if the phase detector polarity is set to negative . charge pump current setting db[27 :2 4 ] set the charge pump current setting (see figure 25 ). s et these bits to the charge pump current that th e loop filter is designed with. prescaler (p/p + 1) the dual - modulus prescaler (p/p + 1) , along with the int, frac , and mod counters, determines the overall division ratio from the rf in to the pfd input. operating at cml levels, it takes the clock from the rf input stage and divides it down for the counters. it is based on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 3 ghz. therefore, when operating the adf4158 above 3 ghz, the prescaler must be set to 8/ 9. the prescaler limits the int value. with p = 4/5, n min = 23. with p = 8/9, n min = 75. rdiv2 setting db 2 1 to 1 inserts a divide - by - 2 toggle flip - flop between the r - counter and the pfd. this can be used to provide a 50% duty cycle signal at the pfd for u se with cycle slip reduction. reference doubler setting db 20 to 0 feeds the ref in si gnal directly to the 5 - bit rf r - counter, disabling the doubler. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding the signal into the 5 - b it r - counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising edge and falling edge of ref in become active edges at the pfd input . the maxi mum allowed ref in frequency when the doubler is enabled is 30 mhz. 5 - bit r - counter the 5 - bit r - counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios fr om 1 to 32 are allowed. 12- bit clk 1 divider bits db[14:3] are used to program the clk 1 divider , which determines the duration of the time step in ramp mode.
adf4158 data sheet rev. i | page 18 of 35 db31 12-bit clk 1 divider 5-bit r counter reserved csr en reserved prescaler cp current setting control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 cr1 cpi4 cpi3 cpi2 cpi1 0 p1 u2 u1 r5 r4 r3 r2 r1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(0) cr 1 cycle slip reduction 0 di s a bl e d 1 en a b le d u 1 reference doubler 0 di s a bl e d 1 en a b le d r 5 r 4 r 3 r 2 r 1 r - count e r di vi d e r a tio 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 . . . . . . . . . . . . . . . 1 1 1 0 1 2 9 1 1 1 1 . 3 0 1 1 1 1 1 3 1 0 0 0 0 0 3 2 u 2 r divi d e r 0 di s a bl e d 1 en a b le d p1 p r esc a l e r 0 4/5 1 8/9 i cp ( m a ) c p i 4 c p i 3 c p i 2 c p i 1 5.1 k ? 0 0 0 0 0.3 1 0 0 0 1 0.6 3 0 0 1 0 0.9 4 0 0 1 1 1.2 5 0 1 0 0 1.5 7 0 1 0 1 1.8 8 0 1 1 0 2.1 9 0 1 1 1 2.5 1 0 0 0 2.8 1 1 0 0 1 3.1 3 1 0 1 0 3.4 4 1 0 1 1 3.7 5 1 1 0 0 4.0 6 1 1 0 1 4.3 8 1 1 1 0 4.6 9 1 1 1 1 5 dbb dbb rdiv2 dbb reference doubler dbb 08728-013 d12 d11 .......... d2 d1 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 notes 1. dbb = double-buffered bits. 12-bit clk 1 divider value figure 25 . r - divider register (r2) map
data sheet adf4158 rev. i | page 19 of 35 function register (r 3) map w ith register r3 db [ 2: 0] set to [0, 1, 1], the on - chip function register is programmed as shown in figure 26. reserved bits all reserved bits should be set to 0 for normal operation. n sel this setting is used to circumvent the is sue of pipeline dela y between an update of the integer and fractional values in the n - c ounter. typically, the int value is loaded first, followed by the frac value. this can cause the n - counter value to be at an incorrect value for a brief period of time e qual to the pipeline delay (about four pfd cycles ) . this has no effect if the int value has not been updated. however , if the int value has been changed , this can cause the pll to overshoot in frequency while it tries to lock to the temporarily incorrect n value. after the correct fractional value is loaded, the pll quickly lock s to the correct frequency. introducing an additional delay to the loading of the int value using the n sel bit cause s th e int and frac value s to be loaded at the same time , preventi ng frequ ency overshoot. the delay is t urned on by setting bit db 15 to 1. sd reset for most applications, db14 should be set to 0. when db14 is set to 0, the - modulator is reset on each write to register r 0. if it is not required that the - modulator b e reset on each register r 0 write, set this bit to 1. ramp mode db [ 11 :10] determine the type of generated waveform. psk en able when db9 is set to 1 , psk modulation is enabled . when set to 0, psk modulation is disabled. fsk en able when db8 is set to 1 , fsk modulation is enabled . when set to 0, fsk modulation is disabled. lock detect precision (ldp) when db7 is programmed to 0, 24 consecutive pfd cycles of 15 ns must occur before digital lock detect is set. when this bit is programmed to 1, 40 consecutive ref erence cycles of 15 ns must occur before digital lock detect is set. phase detector (pd) polarity db6 sets the phase detector polarity. when the vco characteristics are positive, set this bit to 1. when the vco characteristics are negative, set this bit t o 0. power - down db5 provides the programmable power - down mode. setting this bit to 1 performs a power - down. setting this bit to 0 returns the synthesizer to normal operation. while in software power - down mode, the part retains all information in its regist ers. only when supplies are removed are the register contents lost. when a power - down is activated, the following events occur: 1. all active dc current paths are removed. 2. the synthesizer counters are forced to their load state conditions. 3. the charge pump is forced into three - state mode. 4. the digital lock - detect circuitry is reset. 5. the rf in input is debiased. 6. the input register remains active and capable of loading and latching data. charge pump three - state db 4 puts the charge pump into three - state mode when pr ogrammed to 1. it should be set to 0 for normal operation. counter reset db3 is the rf counter reset bit . when this bit is set to 1, the rf synthesizer counters are held in reset. for normal operation, set this bit to 0.
adf4158 data sheet rev. i | page 20 of 35 db31 reserved power-down pd polarity ldp counter reset cp three-state control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns1 u12 0 0 rm2 rm1 pe1 fe1 u11 u10 u9 u8 u7 c3(0) c2(1) c1(1) u9 power-down 0 disabled 1 enabled u11 ldp 0 24 pfd cycles 1 40 pfd cycles ns1 n sel 0 n word load on sdclk 1 n word load delayed 4 cycles rm2 ramp mode 0 continuous sawtooth 1 rm1 0 1 single ramp burst 1 0 single sawtooth 0 1 continuous triangular u7 counter reset 0 disabled 1 enabled u10 pd polarity 0 negative 1 positive u8 cp three-state 0 disabled 1 enabled sd reset n sel reserved fe1 fsk enable 0 disabled 1 enabled u12 - reset 0 enabled 1 disabled pe1 psk enable 0 disabled 1 enabled 08728-014 ramp mode psk en fsk en figure 26 . function register (r3) map
data sheet adf4158 rev. i | page 21 of 35 test register (r4) m ap with register r4 db [2 : 0] set to [1, 0, 0], the on - chip test register (r4) is programmed as shown in figure 27. le sel in some applications, it is necessary to synchroniz e le with the r eference signal . to do t his, db 31 should be set to 1. synchronization is done internally on the part. - modulator mode to completely disable the - modulator, set bits db[30:26] to 0b01110, which puts the adf4158 into integer - n mode, and the channel spacing becomes equal to the pfd frequency. both the 12 - bit msb fractional value (register r0, db[14:3]) and the 13- bit lsb fractional value (register r1, db[27:15]) must be set to 0. after writing to register 4, register 3 must be written to twice to trigger a counter reset. (that is, write regist er 3 with db3 = 1, and then write register 3 with db3 = 0.) all features driven by the - modulator are disabled, such as rampi ng, psk, fsk, and phase adjust. disabling the - modulator also removes the fixed + (f pfd /2 26 ) offset on the vco output. for normal operation, set these bits to 0b00000. reserved bits all reserved bits should be set to 0 for normal operation . negative bleed current setting bits db[24:23] to 11 turns on the constant negative bleed current. this ensures that the charge pump operates out of the dead zone. thus, the phase noise is not degrade d and the level of spurs is lower. enabling constant negative bleed current is particularly important on channels close to multiple pfd frequencies. refer to the an - 1154 application note for mor e information on the negative bleed current. when using negative bleed current, readback to muxout must be disabled. readback to muxout db[22:21] enable or disable the readback to muxout function. this function allows reading back the synthesizer s frequen cy at the moment of interrupt. when using readback to muxout, negative bleed current must be off. clock divider (div) mode bits db[20:19] are used to enable ramp divider mode or f ast lock d ivider mode. if neither is being used, set these bits to 0b00. 12- b it clk 2 divider value bits db[18:7] program the clock divider ( the clk 2 timer ) when the part operat es in ramp mode (see the timeout interval section). the clk 2 timer also determines how long the loop remains in wideband mode when fast lock mode is used ( s ee the fast lock mode section). db31 12-bit clk 2 divider value - modulator mode reserved le sel reserved control bits db30 db29 db28 db27 db26 db25 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 ls1 s5 s4 s3 s2 s1 0 r2 r1 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(1) c2(0) c1(0) d12 d11 .......... d2 d1 clock divider value 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 4092 4093 4094 4095 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ck 2 ck 1 clock divider mode 0 0 clock di vider off 0 1 fast-lock divider 1 0 reserved 1 1 ramp divider 0 0 0 0 clk div mode read- back to muxout 08728-115 db24 db23 nb2 nb1 neg bleed curr- ent r2 readback to muxout 0 disabled 1 enabled r1 0 0 nb2 negative bleed current 0 off 1 on nb1 0 1 ls1 le sel 0 1 s2 s3 s4 s5 s1 - modulator mode 0 normal operation 1 0 0 0 0 1 0 1 0 disabled when frac = 0 le from pin le synch with ref in figure 27 . test register (r4) map
adf4158 data sheet rev. i | page 22 of 35 d eviation register (r5) map with register r5 db [2 :0 ] set to [1, 0, 1], the on - chip dev iation register is prog rammed as shown in f igure 28. reserved bits all reserved bits should be set to 0 for normal operation. tx ramp clk setting db29 to 0 us es t he clock divider clock for clocking the ramp. setting db29 to 1 use s the t x data clock for clocking the ramp. par ramp setting db28 to 1 enables the parabolic ramp . s etting db28 to 0 disables the parabolic ramp. interrupt db[27:26] determine which type of interrupt is used. this feature is used for reading back the int and farc value of a ramp at a given moment in time (rising edge on the tx data pin triggers the interrupt). from the se bits, frequency can be obtained . after readback , the sweep might continue or stop at the read back frequency. fsk ramp enable setting db25 to 1 enables the fsk ramp . setting db25 to 0 disables the fsk ramp. ramp 2 enable setting db24 to 1 enables the second ramp . setting db24 to 0 disables the second ramp. deviation select setting db23 to 0 c hooses the first deviation word. setting db23 to 1 chooses the second deviat ion word. 4 - bit deviation offset word db[22:19] determine the deviation offset. the deviation offset affects the deviation resolution. 16- bit deviation word db[18:3] determine the signed deviation word. the deviation word defines the d eviation step. db31 16-b i t d ev i a t io n w o r d c o n t r o l b i t s db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 t r 1 p r 1 i 2 i 1 f r e 1 r 2 e 1 d s 1 d o 4 d o 3 d o 2 d o 1 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 c 3 ( 1 ) c 2 ( 0 ) c 1 ( 1 ) 07828-116 i2 i1 interrupt 0 0 interrupt off 1 1 load channel continue sweep d16 d14 .......... d2 d1 16-bit deviation word 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 1 1 .......... 1 1 ?1 1 1 .......... 1 0 ?2 1 1 .......... 0 1 ?3 1 0 .......... 0 0 ?32,768 d4 d3 d 1 d 2 4 -b i t d ev o ff set w o r d dev sel ramp 2 en fsk ramp en interrupt par ramp pr1 par ramp 0 disabled 1 enabled 0 1 0 1 not used load channel stop sweep fre1 fsk ramp enable 0 disabled 1 enabled r2e1 ramp 2 enable 0 disabled 1 enabled do4 do3 do2 do1 4-bit dev offset word 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 . . . . . . . . . . . . 1 0 0 1 9 ds1 dev sel 0 dev word 1 1 dev word 2 reserved tx ramp clk tr1 tx ramp clk 0 clk div 1 tx data 0 1 .......... 1 1 32,767 . . .......... . . . . . .......... . . . f igure 28 . dev iation register (r5) map
data sheet adf4158 rev. i | page 23 of 35 step register (r6) map with register r6 db [2 : 0] set to [1, 1, 0], the on - chip step register is programmed as shown in figure 29. reserved bits all reserved bits sh ould be set to 0 for normal operation . step sel setting db23 to 0 chooses step word 1 . setting db23 to 1 chooses step word 2. 20- bit step word db[22:3] determine the step word. step word is a number of steps in the ramp. db 3 1 20-bit step word reserved control bits db 3 0 db 2 9 db 2 8 db 2 7 db 2 6 db 2 5 db 2 4 db 2 3 db 2 2 db 2 1 db 2 0 db 1 9 db 1 8 db 1 7 db 1 6 db 1 5 db 1 4 db 1 3 db 1 2 db 1 1 db 1 0 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 0 0 0 0 0 0 0 0 sse 1 s 2 0 s 1 9 s 1 8 s 1 7 s 1 6 s 1 5 s 1 4 s 1 3 s 1 2 s 1 1 s 1 0 s 9 s 8 s 7 s 6 s 5 c 3 ( 1 ) c 2 ( 1 ) c 1 ( 0 ) 08728-117 s 2 0 s 1 9 ......... . s2 s1 c l o ck d i v i d e r v a l u e 0 0 ......... . 0 0 0 0 0 ......... . 0 1 1 0 0 ......... . 1 0 2 0 0 ......... . 1 1 3 . . ......... . . . . . . ......... . . . . . . ......... . . . . 1 1 ......... . 0 0 1048572 1 1 ......... . 0 1 1048573 1 1 ......... . 1 0 1048574 1 1 ......... . 1 1 1048575 s 4 s 3 s 1 s 2 step sel sse 1 s t ep se l 0 s t ep w o rd 1 1 s t ep w o rd 2 figure 29 . step register (r6) map
adf4158 data sheet rev. i | page 24 of 35 d elay register (r7) map with register r7 db [ 2: 0] set to [1, 1, 1], the on - chip delay register is programmed as shown in figure 30. reserved bits all reserved bits should be set to 0 for normal operation. ramp delay fast l ock setting db18 to 1 enables t he ramp delay fast - lock function . setting db18 to 0 disables this function. ramp delay setting db17 to 1 enables the ramp delay function . setting db17 to 0 disables this function. delay clock select setting db 1 6 to 0 selects the pfd clock as the delay clock . setting db16 to 1 selects pfd clk 1 ( clk 1 set by db[14:3] in register r 2) as delay clock. delayed start enable setting db15 to 1 enables delayed start . setting db15 to 0 disables del ayed start. 12- bit delayed start word db[14:3] determine the delay start word. the delay start word affects the duration of the ramp start delay. db31 12-bit del a y s t art word rese r ved contro l bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 rdf1 rd1 dc1 dse1 ds12 ds 1 1 ds10 ds9 ds8 ds7 ds6 ds5 c3(1) c2(1) c1(1) 08728- 1 18 d s1 2 d s1 1 ......... . d s2 d s1 12 -b i t d el a y st ar t w o r d 0 0 ......... . 0 0 0 0 0 ......... . 0 1 1 0 0 ......... . 1 0 2 0 0 ......... . 1 1 3 . . ......... . . . . . . ......... . . . . . . ......... . . . . 1 1 ......... . 0 0 409 2 1 1 ......... . 0 1 409 3 1 1 ......... . 1 0 409 4 1 1 ......... . 1 1 409 5 ds4 ds3 ds1 ds2 dse1 de l s t art enable 0 disable 1 enable de l s t art en de l clk se l ram p de l ram p de l f l rdf1 ram p del a y f ast lock 0 disabled 1 enabled dc1 de l clk se l 0 pfd clk 1 pfd clk 1 rd1 ram p del a y 0 disabled 1 enabled figure 30 . delay register (r7) map
data sheet adf4158 rev. i | page 25 of 35 applications informa tion initialization s equence after powering up the part, administer th e following programming sequence: 1. delay register (r7) 2. step register (r6) load the step register (r6) twice, first with step sel = 0 and then with step sel = 1 3. dev iation register (r5) load the deviation regis ter (r5) twice, first with dev sel = 0 and then with dev sel = 1 4. test register (r4) 5. function register (r3) 6. r - divider register (r2) 7. lsb frac register (r1) 8. frac/int register (r0) rf synthesizer: a wo rked example the following equation governs how the synthes izer should be programmed: rf out = [ n + ( frac/ 2 25 )] [ f pfd ] ( 4 ) where: rf out is the rf frequency output. n is the integer division factor. frac is the fractionality. f pfd = ref in [(1 + d )/( r ( 1 + t ))] (5 ) where: ref in is the reference frequency input. d is the rf ref in doubler bit. r is the rf reference division factor. t is the reference divide - by - 2 bit (0 or 1). for example, in a system where a 5.8002 ghz rf frequency output (rf out ) is required and a 10 mhz reference frequency input (ref in ) is avail able, the frequency resolution is f res = ref in / 2 25 (6) f res = 10 mhz / 2 25 = 0.298 hz from equation 5 , f pfd = [10 mhz (1 + 0)/1] = 10 mhz 5.8002 ghz = 10 mhz (n + frac/ 2 25 ) calculating n and frac values, n = int ( rf out / f pfd ) = 580 frac = f msb 2 13 + f l sb f msb = int (((rf out / f pfd ) ? n) 2 12 ) = 81 f lsb = int (((((rf out / f pfd ) ? n) 2 12 ) ? f msb ) 2 13 ) = 7537 where: f msb is the 12 - bit msb frac value in register r0. f lsb is the 13 - bit lsb frac value in register r1. int () makes an integer of the argument in p arentheses . reference doubler an d reference divider the reference doubler on chip allows the input reference signal to be doubled. this is useful for increasing the pfd comparison f requency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually impr oves noise performance by 3 db. it is important to note that the pfd cannot be operated above 32 mhz due to a limitation in the sp eed of the - circuit of the n - divider. cycle slip reduction for faster lock time s in fast - locking applications, a wide loop filter bandwidth is required for fast frequency acquisition, resulting in increased integrated phase noise and reduced spur attenu ation. using cycle slip reduction, the loop bandwidth can be kept narrow to reduce integrated phase noise and attenuate spurs while still realizing fast lock times. cycle slips cycle slips occur in integer - n/fractional - n synthesizers when the loop bandwidt h is narrow compared with the pfd freq uency. the phase error at the pfd inputs accumulates too fast for the pll to correct, and the charge pump temporarily pumps in the wrong direction, slowing down the lock time dramatically. the adf4158 contains a cycle slip reduction circuit to extend the linear range of the pfd, allowing faster lock times without loop filter changes . when the adf4158 detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. this outputs a constant current to the loop filter or removes a constant current from the loop filter (depending on whether the vco tuning voltage needs to increase or decrease to acquire the new frequency) . the effect is that the linear range of the pfd is increased. stability is maintained because the curr ent is constant and is not a pulsed current. if the phase error increases again to a point where another cycle slip is likely, the adf4158 turns on another charge pump cell. this continues until the adf4158 detects that the vco frequency has gone past the desired frequency. it then begins to tur n off the extra charge pump cells one by one until they are all turned off and the frequency is settled. up to seven extra charge pump cells can be turned on. in most applications, it is enough to eliminate cycle slips altogether, giving much faster lock t imes.
adf4158 data sheet rev. i | page 26 of 35 setting bit db28 in the r - d ivider register ( register r2) to 1 enables cycle slip reduction. note that a 45% to 55% duty cycle is needed on the signal at the pfd in order for csr to operate correctly. the reference divide - by - 2 flip - flop can help to provide a 50% duty cycle at the pfd. for example, if a 100 mhz reference frequency is available and the user wants to run the pfd at 10 mhz, setting the r - divide factor to 10 result s in a 10 mhz pfd signal that is not 5 0% duty cycle. by setting the r - d ivide factor to 5 and enabling the reference divid e - by - 2 bit, a 50% duty cycle 10 mhz signal can be achieved. note that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (db6 in register r3). it cann ot be used if the phase detector polarity is negative. modulation the adf4158 can operate in frequency shift keying (fsk) or phase shift keying (psk ) mode. frequency shift keying (fsk) fsk is imple mented by setting the adf4158 n - divider up for the cente r frequency and then toggling the tx data pi n. the deviation from the cent e r frequency is set by f dev = ( f pfd /2 25 ) ( dev 2 dev_offset ) ( 7 ) w here : f pfd is the pfd frequency. dev is a 16 - bit word. dev_offset is a 4 - bit word. the adf4158 implements this by incrementing or decre menting the set n - divide value by dev 2 dev_offset . phase shift keying (psk) when the adf4158 is set up in psk mode, it is possible to toggle the output phase of the adf4158 between 0 and 180. the tx data pin controls the phase. fsk settings worked example for example, take an fsk system operating at 5.8 ghz, with a 25 mhz pfd, 250 khz d eviation and dev_offset = 4. re arrange equation 4 as follows offset dev pfd dev f f dev _ 25 2 2 = = = dev the dev val ue is rounded to 2 2 tolin the tx data pin ause s the freueny to hop between 25 freuenies from the prorammed ent e r freueny waveform generation the adf4158 is capable of generating four types of waveforms in the frequency domain : single ramp burst, single sawtooth burst, sawtooth ramp, and triangular ramp . figure 31 through figure 34 show th e types of waveforms available. frequency time 08728-022 figure 31 . single ramp burst frequency t i m e 08728-021 figure 32 . single sawtooth burst frequency time 08728-019 figure 33 . sawtooth ramp frequency time 08728-020 figure 34 . tr iangular ramp
data sheet adf4158 rev. i | page 27 of 35 waveform deviations and timing figure 35 shows a version of a burst or ramp. the key parameters that define a burst or ramp are ? frequency deviation ? timeout interval ? number of steps timer f dev frequency time 08728-023 figure 35 . waveform timing frequency deviation the frequency deviation for ea ch frequency hop is set by f dev = ( f pfd /2 25 ) ( dev 2 dev_offset ) ( 9 ) w here : f pfd is the pfd frequency. dev is a 16 - bit word. dev_offset is a 4 - bit word. timeout interval the tim e betwe en each frequency hop is set by timer = clk 1 clk 2 (1/ f pfd ) ( 10) where: clk 1 and clk 2 are 12 - bit clock values (12 - b it clk 1 divider in r2, 12 - bit clock di vider in r4 clk div set as ramp div). f pfd is the pfd frequency . number of steps a 20 - bit ste p value defines the number of frequency hops that take place. the int value cannot be incremented by more than 2 8 = 256 from its starting value. single ramp burst the most basic waveform is the single ramp burst. all other waveforms are slight variations o n this. in the single ramp burst, the adf4158 is locked to the fre - quency defined in the frac/ int register. when the ramp mode is enable d, the adf4158 increments the n - divide value by dev 2 dev_ofset , causing a frequency shift , f dev , on each timer interval. this happens until the set number of steps has taken place. the adf4158 then retain s the final n - divide value. single sawtooth burst in the single sawtooth burst , th e n - divide value is reset to it s initial value on the next timeout interval after the number of steps has taken place. the adf4158 retains this n - divide value. sawt ooth ramp the sawtooth ramp is a repe ated version of the single saw tooth burst. the waveform repeats until the ramp is disabled. triangular ramp the triangular ramp is similar to the single ramp burst. howe ver , when the steps ha ve been completed, the adf4158 begins to decrement the n - divide value by dev 2 dev_offset on each timeout interval. when the number of steps has again been completed, it rever ts to incrementing the n - divide value. repeating this creates a triangular waveform. the waveform repeats until the ramp is disabled. fmcw radar ramp settings worked example ta ke as an example , a n fmcw radar system requiring the rf lo to sawtooth ramp ove r a 50 mhz range every 2 ms. the pfd frequency is 25 mhz, and the rf output range is 5800 mhz to 5850 mhz. the f requency deviation for each hop in the ramp is set to ~250 khz. the frequency resolution of adf4158 is calculated as follows: f res = f pfd /2 25 ( 11) numerically: f res = 25 mhz/2 25 = 0.745 hz the dev_offset is calculated after rearranging equation 9 : dev_offset = log 2 ( f dev / ( f res dev max )) (12 ) expressed in log 10 (x) , equation 10 can be transformed into the following equation: dev_offset = log 10 ( f dev /( f res dev max ))/log 10 (2) (1 3 ) where: dev_offset = a 4 - bit word. f dev = frequency deviation. dev max (maximum of the deviation word) = 2 15 using e quation 1 3 , dev_offset is calculated as follows dev_offset = log 10 (250 khz / (0.745 hz 2 15 ))/log 10 (2) = 3.356 after rounding , dev_offset = 4 . from dev_offset , the resolution of frequency deviati on can be calculated as follows f dev_res = f res 2 dev_offset (14) f dev_res = 0.745 hz 2 4 = 11.92 hz
adf4158 data sheet rev. i | page 28 of 35 t o calculate the dev word , use equation 1 5 . dev = f dev / ( f res 2 dev_offset ) (15) 52 . 971 , 20 2 2 mhz 25 z kh 250 4 25 = = dev roundin this to 2 2 and realulatin usin euation to et the atual deviation freueny f dev thus produes the followin f dev = (25 mhz/2 25 ) (20 , 972 2 4 ) = 250.006 khz the number of f dev steps required to cover the 50 mhz range is 50 mhz/250.006 khz = 200. to cover the 50 mhz range in 2 ms, the adf4158 must hop every 2 ms/200 = 10 s. rearrang e equa tion 10 to set the timer value (and fix clk 2 to 1): clk 1 = timer f pfd / clk 2 = 10 s 25 mhz /1 = 250 to summarize the settings: dev = 20 , 972, n umber of steps = 200, clk 1 = 250 (12 - bit clk 1 divider in r2) , clk 2 = 1 (r4 clk div set as ramp div) . using these settings, program the adf4158 to a cent e r frequency of 5800 mhz, and enabl e the sawtooth ramp to produce the required waveform. if a triangular ramp was used with the same settings, the adf4158 would sweep from 5800 mhz to 5850 mhz and back down again. the entire sweep would take 4 ms. activating the ramp after setting all of the previous parameters , the ramp must be activated. it is achieved by choosing the desired type of ramp (db[11 :10] in register r 3) and starting the ramp (db 31 = 1 in reg ister r 0) . ramp programming sequence set parameters as described in the fmcw radar ramp settings worked example section and activate the ramp as described in the activating the ramp section in the following register write order. 1. delay register (r7) 2. step register (r6) 3. deviation register (r5) 4. test register (r4) 5. function register (r3) 6. r - divider register (r2) 7. lsb frac register (r1) 8. frac/int register (r0) other waveforms two ramp rates this feature allows for two ramps with different step and deviation settings. it also allows the ramp rat e to be reprogrammed while an other ramp is running. example if , for example ? pll is locked to 5790 mhz and f pfd = 25mhz . ? ramp 1 jumps 100 steps , each of which lasts 10 s and has a frequency deviation of 100 khz. ? ramp 2 jumps 80 steps , each of which lasts 10 s and has a f requency deviation of 125 khz. then, 1. db24 in register r 5 should be set to 1 , which activates r am p 2 rates mod e. 2. program ramp 1 and ramp 2 as follows to get two ramp rates : ramp 1 : register r 5 db [18:3] = 16 , 777, db[22:19] = 3 with db23 = 0; register r 6 db[22:3] = 100, db23 = 0. ramp 2 : register r 5 db[18:3] = 20 , 972, db [22:19] = 3 with db23 = 1; regi ster r 6 db[22:3] = 80, db23 = 1. the resulting r amp with two various rates is shown in figure 36. eventually , the ramp must be activated as described in the activating the ramp section. frequency time sweep rate set by other register sweep rate set by one register 08728-024 figure 36 . dual sweep rate ramp mode with fsk signal on ramp in traditional approach es a fmcw radars used either l inear f requency m odulation (lfm ) or fsk modulation. these modulations used separately introduce ambiguity between measured distanc e and velocity, especially in multitarget situations. t o overcome this issue and enable unamb iguous (range ? velocity) multi target detection , use a ramp with fsk on it . example if, for example ? pll is locked to 5790 mhz. f pfd = 25mhz ? there are 100 steps ea ch of which lasts 10 s and has a deviation of 100 khz. ? the fsk signal is 25 khz. then, 1. program the ramp as described in the fmcw radar ramp settings worked example section . while doing that db23 in register r 5 and db23 in registe r r 6 should be set to 0. 2. set the bits in register r5 as follows to program fsk on ramp to 25 khz : db[18:3] = 4194 (deviation word), db[22:19] = 3 (deviation offset), db23 = 1 (deviation select for fsk on ramp) , and db25 = 1 (ramp with fsk enabled).
data sheet adf4158 rev. i | page 29 of 35 an exam ple of ramp with fsk on the top of it is shown in figure 37. eventually , the ramp must be activated as described in the activating the ramp section. 08728-025 frequency 0 ramp end frequency sweep fsk shift time lfm step = frequency sweep/number of steps figure 37 . combined fsk and lfm waveform (n corresponds to the number of lfm steps ) delayed start a delayed start can be used with two different parts to control the start time. the idea of delayed start is shown in figure 38. frequency time ramp with delayed start ramp without delayed start 08728-126 figure 38 . delayed start of sawtooth ramp example for example, to program a delayed start with two different parts to control the start time, 1. set db15 in register r 7 to 1 to enable the delayed start of ramp option. 2. set bit db16 in register r 7 to 0 a nd the 12 - bit delay start word (db[ 14:3 ] in register r 7) to 125 to delay the ramp on the first part is delayed by 5 s , f pfd = 25 mhz . the delay is calculated as follows: delay = t pfd delay start word = 40 ns 125 = 5 s 3. set bit db16 in regist er r 7 to 1 and the 12 - bit delay start word (db[ 14:3 ] in register r 7) to 125 to delay the ramp on the second part is delayed by 125 s. u se the following formula for calculating the delay: delay = t pfd clk 1 delay start word = 40 ns 25 1 25 = 125 s eventually , the ramp must be activated as described in the activating the ramp section. delay between ramps this feature adds a delay between bursts in ramp. figure 39 show s a delay between ramps in sawtooth mode. frequency t i m e d e l a y 08728-028 figure 39 . delay between ramps for sawtooth mode example for example, to add a delay between bursts in a ramp, 1. set db 1 7 in register r 7 to 1 to enable delay between ramps option. 2. set bit db16 in register r 7 to 0 and the 12 - bit delay start word (db[14 :3 ] in register r 7) to 125 to delay the ramp by 5 s , f pfd = 25 mhz . the de lay is calculated as follows: delay = t pfd delay start word = 40 ns 125 = 5 s if a longer delay is needed, for example , 125 s, bit db16 in register r 7 should be set to 1 and the 12 - bit delay start word ( db[ 14:3 ] in register r 7) should be set to 125. the d elay is calculated as follows delay = t pfd clk 1 delay start word = 40 ns 25 125 = 125 s there is also a possibility to activate fast - lock operation for the first period of delay. this is done by setting bit db18 in register r 7 to 1. this feature is useful for saw tooth ramps to mitigate the frequency overshoot on the transition from one saw tooth to th e next . eventually , the ramp must be activated as described in the activating the ramp section. nonl inear ramp mode the ad f4158 is capable of generating a parabolic ramp. the output frequency is generated according to the following equation : f out ( n + 1) = f out ( n) + n f dev ( 16) where: f out is output frequency . n is step number. f dev is frequency deviation . frequency t i m e 08728-029 figure 40 . parabolic ramp
adf4158 data sheet rev. i | page 30 of 35 the following example explains how to set up and use this function. example f out = 5790 mhz f dev = 100 khz number of steps = 50 duration of a single step = 10 s ramp mode must be either triangular ( register r3 , db[1 1:10] = 01) or single ramp burst ( register r3 , db[11:10] = 11). in the first case , the generated frequency range is calculated as follows: f = f dev ( number of steps + 2) ( number of steps + 1)/2 = 132.6 mhz in the second case , the generated frequency range is calculated as follows: f = f dev ( number of steps + 1) number of steps /2 = 127.5 mhz the timer is set in the same way as for its linear ramps described in the waveform generation section . activation of the parabolic ramp is achieved by setting bit db28 in register r 5 to 1 . next the counter reset (db3 in regi ster r 3) should be set first to 1 and then to 0 . eventually , the ramp must be activated as described in the activating the ramp section. ramp complete signal t o m uxout ramp complete signal on muxout is shown in figure 41. 08728-100 time time vo lt age frequenc y figure 41 . ramp complete signal on muxout t o activate this function db[30:27] = 1111 in register 0 and db[25:21] = 00011 in register 4 . external control of ramp steps the internal ramp clock can be bypassed and each step can be triggered by a pulse on the tx data pin. this allows for more transparent control of each step. enable this feature by setting bit db29 in register r5 to 1. frequenc y time tx d at a rf out vo lt age time 08728-148 figure 42 . external control of ramp steps interrupt modes and frequency readb ack interrupt modes are triggered from the rising edge of tx data . depending on the settings of db[ 27:26 ] in regist er r 5, the modes in table 7 are activated. table 7. interrupt modes mode action db[27:26] = 00 interrupt is off db[27:26] = 01 interrupt on tx data , sweep continues db[27:26] = 11 interrupt on tx data , sweep stops when an interrupt takes place, the data consisting of the int and frac value s can be read back via muxout. the data is made up of 37 bits, 12 of which r epresent the int value and 25 the frac value. the idea of frequency readback is shown in figure 43.
data sheet adf4158 rev. i | page 31 of 35 frequency logic level time time time of interrupt frequency at which interrupt took place interrupt signal logic high logic low 1. sweep continues mode 2. sweep stops mode 1 2 08728-030 figure 43 . interrupt and frequency readb ack n ote that db[2 2 :21] in register r 4 should be set to 0b10 a nd db[30:27] in register r 0 (muxout control ) should be set to 15 (1111) . the mechanism of how single bits are read back is shown in figure 44. for continuous frequency readback the following sequence should be used: ? register 0 write ? le high ? pulse on tx data ? frequency readback (as described at the beginning of the interrupt modes and frequency readb ack section and figure 44) ? pulse on tx data ? register r4 write ? frequency readback ( as described at the beginning of the interrupt modes and frequency readb ack section and figure 44) ? pulse on tx data ? the sequence is also shown in figure 45. 08728-101 muxout clk le tx d at a data clocked out on positive edge of clk and read on negative edge of clk readback word (37 bits) 0 0001 1100 1111 0110 0010 0011 1010 0111 1000 (hex 01cf623a78) lsb msb 12-bit integer word 0000 11 10 0 11 1 0x0e7 231 25-bit frac word 1 0 1 10 0010 00 1 1 1010 0 11 1 1000 0x1623a78 23214712 rf = f pfd (231 + 23214712 2 25 ) = 5.7922963ghz figure 44 . reading back single bits to determine the output frequency at the moment of interrupt clk muxout le tx data data r0 write r4 write r4 write frequency readback frequency readback frequency readback 37 clk pulses 37 clk pulses 37 clk pulses 32 clk pulses 32 clk pulses 32 clk pulses 08728-144 figure 45 . continuous frequency readback
adf4158 data sheet rev. i | page 32 of 35 fast lock mode the adf4158 can operate in fast lock mode. in this mode, the charge pump current is boosted and additional resistors are connected to maintain the stability of the loop. fast lock timer and register sequences when fast lock mode is enabled (register r4, db[2 0:19]), after a write to register r0, the pll operates in a wide bandwidth mode for a selected amount of time. before fast lock is enabled, the initialization sequence must be performed after the part is first powered up (see the initialization s equence section). the time in bandwidth mode is set by: clk 1 clk 2 / f pfd = time in wide b andwidth where: clk 1 = register r2, db[14:3]. clk 2 = register r4, db[18:7]. f pfd = the pfd frequency. note that the fast lock feature does not work in ramp mode. fast lock example in this example, the pll has f pfd of 100 mhz and requires being in wide bandwidth mode for 12 s. clk 1 clk 2 / f pfd = 12 s clk 1 clk 2 = (12 10 ?6 )(100 10 6 ) = 1200 therefore, clk 1 = 12 and clk 2 = 100, which results in 12 s. fast lock loop filter topology to use fast lock mode, an extra connection from the pll to the loop filter is needed. the damping resistor in the loop filter must be reduced to ? of its value in wide bandwidth mode. this reduc tion is r equired because the charge pump current is increased by 16 in wide bandwidth mode, and stability must be ensured. to further enhance stability and mitigate frequency overshoot during a frequency change in wide bandwidth mode, resistor r3 is connected (see figure 46 ). during fast lock, the sw1 pin is shorted to ground, and the sw2 pin is connected to cp (set bits db[20:19] in register r4 to 01 for fast lock divider). the following two topologies can be used: ? divide the damping res istor (r1) into two values (r1 and r1a) that have a ratio of 1:3 (see figure 46). ? connect an extra resistor (r1a) directly from sw1 (see figure 47 ). the extra resistor must be selected such that the paral lel combination of an extra resistor and the damping resistor (r1) is reduced to ? of the original value of r1. for both topologies, the ratio r3:r2 must equal 1:4. vco cp c1 c2 c3 r3 r2 r1 r1 a sw2 sw1 adf4158 08728-032 figure 46 . fast - lock loop filter topology topology 1 vco cp c1 c2 c3 r3 r2 r1 r1a sw2 sw1 adf4158 08728-102 figure 4 7 . fast - lock loop filter topology ? topology 2 for more fast lock topologies, see adisimpll .
data sheet adf4158 rev. i | page 33 of 3 5 spur mechanisms the fractional interpolator in the adf4158 is a third - order - modulato r (sdm) with a 25 - bit fixed modulus (mod). the sdm is clocked at the pfd reference rate (f pfd ) that allows pll output frequencies t o be synthesized at a channel step resolution of f pfd / mod. the various spur mechanisms possible with fractional - n synthesizers and how they affect the adf4158 are discussed in this section. fractional spurs in most fractional synthesizers, fractional spurs can appear at the set channel spacing of the synthesizer. in the adf4158 , these spurs do not appear. the high value of the fixed modulus in the adf4158 makes the sdm quantization error s pectrum look like broadband noise, effectively spreading the fractional spurs into noise. integer boundary spurs interactions between the rf vco frequency and the pfd frequency can lead to spurs known as integer boundary spurs. when these frequencies are n ot integer related (which is the p urpose of the fractional - n synthesizer), spur sidebands appear on the vco output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the pfd and the vco frequency. these spurs are named integer boundary spurs because they are more noticeable on channels close to integer multiples of the pfd where the difference frequency can be inside the loop bandwidth. these spurs are attenuated by the loop filter on ch annels far from integer multiples of the pfd. reference spurs reference spurs are generally not a problem in fractional - n synthesizers because the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechanism that bypasse s the loop can cause a problem. one such mechanism is the f eedthrough of low levels of on - chip reference switchi ng noise out through the rf in pin s back to the vco, resulting in reference spur levels as high as ? 90 dbc. ta ke c are in the printed circuit board ( pcb ) layout to ensure that the vco is well separated from the input reference to avoid a possible feedthrough path on the board. low frequency applic ations the s pecification on the rf input is 0.5 ghz minim um; howev er, rf frequencies lower than this can be used if the minimum slew rate specification of 400 v/s is met. an appropriate lvds drive r can be used to square up the rf signal before it is fed back to the adf4158 rf input. the fin1001 from fairchild semiconductor is one such lvds driver. filter design adi sim pll a filter design and analysis program is available to help the user implement pll design. visit http://www.analog.com/pll for a free download of the adisimpll software. this software designs, simulates, and analyzes the entire pll frequency domain and time domain response. various passive and active fi lter architectures are allowed. pcb design guideline s for the chip scale package the lan ds on the chip scale package (cp - 24) are rectangular. the pcb pad for thes e should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. center t he land on the pad . this ensures that the solder joint size is maximized . the bottom of the chip scale package has a central thermal pad. the thermal pad on the pcb should be at least as large as this exposed pad. on the pcb , there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, they should be incorporated into the thermal pad at 1.2 mm pitch grid. the via diameter sh ould be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ou nce of copper to plug the via. c onnect the pcb thermal pad to agnd.
adf4158 data sheet rev. i | page 34 of 35 application of adf4158 in fmcw radar the adf4158 in fmcw radar is used for generating ramps (sawtooth or triangle) that are necessary for this type of radar to operate. traditionally, the pll was driven directly by a direct digital synthesizer (dds) to generate the required type of waveform. due to the implemented waveform generating mechanism on the adf4158 , a dds is no longer needed, which reduces cost. in addition, the pll solution has advantages over another method (the dac driving the vco directly) for generating fmcw ramps, which suffered from vco tuning characteristics nonlinearities requiring compensation. the pll method gives highly linear ramps without the need for calibration. the application of adf4158 in fmcw radar is shown in figure 48. 08728-034 linear frequency sweep no dds required with adf4158 reference oscillator 26mhz vco adf4158 pll 5 multiply 15 3 pa tx antenna rx antennas 76.5ghz to 77.0ghz 5.1ghz to 5.1333ghz micro- controller 16b 10b to 12b bus can/flexray range compensation baseband mixer dsp adsp-bf531 ad9288 ad9203 ad9235 mux amp adc hpf figure 48. fmcw radar with adf4158
data sheet adf4158 rev. i | page 35 of 35 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant t o jedec standards mo-220-wggd. bot t om view top view side view expose d p a d 4.10 4.00 sq 3.90 0.80 0.75 0.70 0.20 ref 0.20 min 3.16 min coplanarity 0.08 pin 1 indic a t or 2.65 2.50 sq 2.45 1 2 4 7 12 13 18 19 6 0.05 max 0.02 nom pkg-004462 10-19-2017-b sea ting plane pin 1 indic a t or area options (see detail a) detail a (jedec 95) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 49 . 24 - lead lead frame chip scale package [lfcsp ] 4 mm 4 mm body and 0.75 mm package height (cp - 24 - 7 ) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package des cription package option ADF4158CCPZ ?40c to +125c 24- lead lead frame chip scale package [lfcsp] cp -24-7 ADF4158CCPZ - rl7 ?40c to +125c 24- lead lead frame chip scale package [lfcsp] cp -24-7 adf4158wccpz ?40c to +125c 24 - lead lead frame chip scale pa ckage [lfcsp] cp - 24 - 7 adf4158wccpz - rl7 ?40c to +125c 24- lead lead frame chip scale package [lfcsp] cp -24-7 eval - adf4158eb1z evaluation board 1 z = rohs compliant part. 2 w = qualified for automotive applications . automotive products the adf4158w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices accou nt representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2010 C 2018 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08728 - 0 - 6/18(i)

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